Switching Fundamentals: Hysteretic Control

Published: 2024/08/24

In this series, I've introduced what load dump is, what it's used for, and some methods of generating it for testing purposes. In the next section, I'll show the complete design of a powerful, compact and highly flexible generator, but in preparation, I want to first introduce a simple yet effective switching controller that can be used to operate it.

Here, I'll introduce readers to switching circuits, by way of a very rudimentary type of control, which can be built easily (relatively few transistors/ICs), while also demonstrating it "at scale" in a high-power circuit; and, operating in a pulsed mode (as the generator), deeper engineering challenges like thermal management can be largely avoided. This article is also a good introduction by itself, for readers looking for an analytical approach to switching power supply topics.

Automotive Load Dump Introduction
Switching Fundamentals: Hysteretic Control [here]
Automotive Load Dump Switching Generator

Analysis

Suppose we take a basic linear pass-device amplifier:

Source Follower Amplifier

Suppose we overdrive it, such that it turns on (saturation) and off (cutoff) alternately (don't worry how, for the moment), and add a filter to the output. We would have the basic buck converter:

Basic Buck Switching Circuit

Note the catch diode, necessary to conserve inductor current at turn-off, allowing it to circulate through the load. This constrains the voltage on SW to between VIN and GND (less device voltage drops), and in the condition where L is modest and C is large compared to RL, we get simple waveforms: square voltage and triangular inductor current.

Basic Buck Switching Waveforms

Assume the drive signal is periodic, a simple square wave of adjustable duty cycle and frequency. We write down the equations: $\frac{dI}{dt} = \frac{V_{in} - V_o}{L}$ during 0 to DT while Q is on, and $\frac{dI}{dt} = \frac{-V_o}{L}$ during DT to T while D is on. Since the waveforms are straight lines, we change ds to Δs, substitute in the times as labeled, and have:

$I_{pp} = I_p - I_v = \left( V_{in} - V_o \right) \frac{{DT}{L} = V_o \frac{(1 - D)T}{L}$

(That's p for "peak", v for "valley", and pp for "peak-to-peak".) These are equated because the slopes are equal height and opposite direction: this gives the continuity condition for steady-state output current I_o, or equivalently, the condition for net-zero change of flux in L. This holds as long as D is on for the full flyback period, i.e. I_v > 0, which we call continuous conduction mode (CCM). (For simplicity, I'll skip over the alternative case: DCM (discontinuous), where inductor current goes to zero, and switch-node voltage returns to V_o, inbetween conduction phases.) (Also, just to note: since this is steady state, output/load and average inductor current are identical; in general, these can vary, and won't be equal in motion (the difference going into the capacitor), but I'll get to control dynamics later.) Rearranging, we solve V_o = D V_in, and I_o remains a free variable: we conclude that the buck converter should have good regulation, i.e. output voltage varies little (ideally, none) as load current changes. At least, at DC, for the voltage-mode case (i.e. fixed PWM).

We can solve the dynamics, for this fixed PWM case, right now: SW acts like a Thévenin source of very low resistance (more or less, R_DS(on)). For all other frequencies than as-driven (i.e., orthogonal frequencies), it has zero voltage, so acts like a short circuit. Thus, we expect an output response corresponding to L and C in parallel: at DC, the output resistance is small; at frequencies below resonance, inductance dominates; at resonance, impedance is very high; above resonance, capacitance dominates. This wouldn't make a good power supply, and we would at least want something to dampen the LC resonance—perhaps enough ESR in the capacitor to kill the Q factor, but that also costs high-frequency attenuation, so it's not the best.

For hysteretic control, we don't generate PWM per se, but rather switch on and off arbitrarily, as needed to maintain current within some margin. D and T are thus "solved" by the controller, and we have inductor current well-defined. Consider the circuit:

Hysteretic Controller

We have a comparator, U1, driving the switch Q, a MOSFET, at some excess V_GS(on) = V_cc when high, and 0 when low. We take some of the drive voltage back to the noninverting input via resistor divider R_f, R_i to implement hysteresis. We have a current sense shunt resistor R_s, amplified by A (or any equivalent arrangement: a high-side shunt resistor in series with L and a differential amplifier, a Hall effect sensor, etc.). Also assume: R_s is small relative to L, C and RL; the voltage on G and ratio R_f / R_i can be rolled into a fixed hysteresis band (which in general can be independent of both supplies shown); the comparator has some delay t_d; and the comparator's output is fast and strong enough so that the gate rise/fall time is negligible.

Hysteretic Controller Waveforms

Let V_h be the hysteresis voltage, applied symmetrically to V_ref. I_p, I_v, etc. and the edge times 0, DT and T (not marked on this diagram) remain as above. Equations are similar, but note that the comparator internally switches upon crossing the ±V_h/2 thresholds, but Q does not switch until t_d later, thus the peaks overshoot by ΔI = V_L t_d / L. Solving for the peaks, then taking the average of them, we get the steady-state output,

$I_o = \frac{V_{ref}}{A R_s} + \left( \frac{V_{in}}{2} - V_o \right) \frac{t_d}{L}$

We get the expected proportion to V_ref, but also two errors from it: one proportional to V_in (PSRR, as transresistance), and the other to V_o (output resistance; note, the negative sign does not mean negative output resistance, as the sign convention is outward here). Note that, since this is a current regulator, we should want high output resistance, suggesting large L and low t_d are preferable. We can also solve for the period,

$T = \left( \frac{L}{A R_s}\frac{V_{h}}{V_{in}} + t_d \right) \frac{{V_{in}}^2}{ V_o \left( V_{in} - V_o \right) }$

which is mostly proportional to L and V_h as expected, but t_d is also adding in. The duty cycle factor on the right, has a value of 4 when V_o = V_in/2, and grows for other voltage ratios, so the left side is quadrupled at a minimum. Adding hysteresis and t_d makes sense, as it takes one hysteresis band for the comparator to decide, one delay for the output to switch, another delay to recover from that overshoot; and double again for the opposite phase. Thus we should have a minimum period, running flat out, no hysteresis, of 4 t_d, which checks out (assuming of course that this is the only oscillating mode; an ideal propagation delay has infinite, but we can use a bandwidth-limited delay that enforces this). T diverges as V_o → 0 or V_in; this is one of the downsides of hysteretic controllers: the variable frequency makes it hard to design input/output filters, for example, or makes it desirable to limit operation to a modest voltage range (say 15-85% of V_in for frequency in a 2:1 range).

This also explains the stipulation for CCM: if V_ref < V_h/2, it never switches back on again; it's practically forced to operate in CCM, actually (the delay can carry it into DCM however), or it just stops completely. If we put this inside an outer voltage-regulating loop, we will have a dead band where no switching occurs below this threshold, and the outer loop goes unstable—basically, it starts hunting around to maintain regulation. Which on the downside, will increase output voltage ripple, but on the upside, gives us an ad-hoc burst-mode behavior.

Note that inductor current is bounded by the switching thresholds V_ref ± V_h/2 (plus some "slop" due to t_d) and the feedback gain R_s A, so we've immediately resolved one design concern: limiting switch current. Current is bounded for all bounded inputs, and in particular we can construct V_ref such that it saturates within a design range, and therefore inductor current will never be far beyond those bounds. If Q and D are selected (and heatsunk) so as to handle this current under all expected conditions (duty cycle, time at current), we can guarantee reliable operation with respect to that one operating parameter—that is, we've completely solved failure due to excessive current. They can still fail by overheating from switching losses, or overvoltage if the switching speed is too fast for the layout, but one out of three failure mechanisms solved is nothing to sneeze at!

Conversely: while I_o is well defined, V_o is not: merely I_o R_L, so we have no output regulation as such; indeed, it's more of a current source. Which, is what a current-mode control should do, control the current somewhere—so it's doing that well. If we want a stable output voltage, we need another mechanism to enforce that—wrapping the system in another error amp, to automatically set V_ref to control output voltage, for example.

Now, the load dump generator won't require current-mode control for several reasons. But we should still start with current mode, even for the hysteretic case, because it's the simplest, most direct one: the switch controls inductor current, so we feed back on inductor current, period. The analysis is straightforward: we only need to worry about current waveform (simple slopes) and node voltages. Whereas with a voltage-mode control, we would have to know the filter capacitance, probably require ESR in it, and response will be sensitive to the load.

Experimental

The following circuit was built up on breadboard:

U2A and related components constitute the hysteretic comparator, with VR2 the feedback voltage (A = 1, trivially removing the amplifier). Q2 augments U2A's output into a fully-driven source, a common addition with these open-collector comparators. OUT is the internal comparator output; it's fed to a slew-rate limiting circuit of a familiar old design: the full-wave rectifier plus current sources motif features prominently in a number of Tektronix instruments from the 1960s onward, for example. The current from Q1 and Q7, steered by diodes D2, D3, D5 and D6, sets the voltage slope on C5. U2B has a simple midpoint threshold so that, as the slewing crosses VCC/2, the output changes, thus implementing the time delay. Since supply voltage is low, U2B can also serve as level shifter, up to a bootstrap gate driver, D1, Q3, Q4 and Q6. Q5 is the output switch, with minor EMI treatments to clean up the waveforms (modest-value gate resistor, ferrite bead). The output network remains as above.

Top view of the breadboard. A fairly snug fit on a small sized board, but it does the job. Note that Q5, C2 and D7 are co-located to minimize the switching loop area, and those positions on the ground strip act as star grounding for the control circuit. Power input is from the left (RED/BLK), and load is connected on the right (RED/BLU). Some oscilloscope and multimeter probes are clipped onto relevant nodes.

The following waveforms were taken at VREF = 237mV, VR1 = 339mV (Io = 0.5A), VIN = 15.7V and VO = 4.956V (RL about 9.2Ω).

OUT to SW rising edge

OUT (Ch2) and SW (Ch3), rising and faling edge delays. SW risetime is 88ns, fall 24ns; though simple, the gate driver is doing its job, not that IRF510 is a big load, either. The falling edge has 3Vpk ringing at 60MHz, with a Q of about 2 (invisible at this scale); the Q was about 10-15 without the ferrite bead.

OUT and DLY waveforms

OUT (Ch2) and DLY (Ch3). The step due to C6's positive feedback is quite strong with the lowish value of C5.

VR1 and SW waveforms

RS1 (Ch2) and SW (Ch3). (Some error in the peaks of Ch2 are due to the stray field around L1.)

18 trials were measured, over a range of conditions: VIN from 12.65 to 19V, VO from 2.624 to 12.75V, and I_o from 0.18 to 1.13A. Measurements were: DCV of VREF, VIN, VO and VR1; VR1 peak (min, max); and SW frequency and on-time. 20MHz bandwidth limit was used to reduce noise and peak measurement error. The propagation delay between OUT and SW was measured in 12 of the trials:

Propagation delay plot

Columns in random order; vertical axis is propagation delay in μs. Data were collected from the first 12 trials, and found satisfactory enough that the remainder were skipped. We conclude that the delay section is doing its job as intended. Note that there is also ∼300ns from U2A, and 1μs from R19/C9 (quick derivation test: prove that the time shift of an RC lowpass filter, for a ramp input, equals the RC time constant, independent of ramp rate), so we expect the average total to be around 3.6μs.

To prove out the control law, first let's revisit the analysis. Customizing it for the circuit, we find a few new terms:

$T = \left( \frac{L}{A R_s}\frac{V_{h}}{V_{in}} + t_d \right) \frac{{V_{in}}^2}{ V_o \left( V_{in} - V_o \right) }$

and a lot more terms on the input side,

${V_{ref}}^\prime = V_{ref} \frac{r_f}{r_i + r_f} + \frac{V_{OH} + V_{OL}}{2} \frac{r_i}{r_i + r_f}$

This is written as an adjustment to V_ref, as it's mostly biasing of the input due to the feedback resistors R_f and R_i (R13 and R11). V_OH and V_OL are the comparator's output levels (as measured at OUT), and V_F is the rectifier's forward drop. MOSFET R_DS(on) is not included, which is perhaps a poor decision given the relatively high resistance of IRF510.

Rearranging this to the multi-linear expression,

$I_o = I_{offs} + G_{ref} V_{ref} + G_{in} V_{in} + G_{o} V_{o}$

gives quite good fitness, so the general approach seems correct; that leaves only the coefficients in question. We find the following:

Predicted

Measured

Parameter	Value	Unit
I_offs	0.1284	A
G_ref	1.4398	S
G_in	0.0081	S
G_o	-0.0162	S
RMS error	0.0496	A

Parameter	Value	Unit
I_offs	0.0505	A
G_ref	1.3356	S
G_in	0.0128	S
G_o	-0.0157	S
RMS error	0.0181	A

Measurement consists of setting up the above equation, an error function comparing its result to each measured point (in terms of I_o), and using least-squares regression to obtain best-fit parameters.

Constraining I_offs to the calculated value and solving for Gs, found values close to predicted, for G_in (0.0085) and G_o (-0.0155), but G_ref still differs significantly (1.3171); fitness wasn't bad (0.0218 RMS).

A 2nd-order best-fit was also calculated:

$I_o = I_{offs} + G_{ref} V_{ref} + G_{in} V_{in} + G_{o} V_{o} + \\ \Gamma_{rr} {V_{ref}}^2 + \Gamma_{ii} {V_{in}}^2 + \Gamma_{oo} {V_{o}}^2 + \Gamma_{ri} V_{ref} V_{in} + \Gamma_{ro} V_{ref} V_{o} + \Gamma_{io} V_{in} V_{o}$

This is a lot of parameters compared to the sample size, so overfitting is likely; the product terms remain small, at least:

Parameter	Value	Unit
I_offs	-0.1728	A
G_ref	1.1701	S
G_in	0.0424	S
G_o	-0.0062	S
Γ_rr	0.0238	S/V
Γ_ii	-0.00089	S/V
Γ_oo	-0.00050	S/V
Γ_ri	-0.0044	S/V
Γ_ro	-0.0135	S/V
Γ_io	-0.00053	S/V
RMS error	0.0158	A

As no product terms arise in, at least the relatively simple derivation above—I don't have much to interpret here. Γ_rr could be justifiable as I_o to V_in feedback (via R_DS(on), quadratic as current compounds during the cycle), and perhaps Γ_ro for the same reason (since on-time is dependent on output voltage). Perhaps quadratic (and still higher-order) terms arise as an expression of rational terms, such as relates to duty cycle (i.e., of the form a / (a + b)). Perhaps Γ_ii could be affected by non-ideal quirks of the circuit, like timing variation, rise/fall time dependent on supply voltage, etc.

Output frequency and on-time (expressed as duty cycle) were also modeled, and used to extract an effective overall time delay and diode forward voltage. The above equation for cycle period, or rather its reciprocal, was compared to measured frequency, and this used to determine t_d and V_F. The duty formula is sensitive only to V_F, while frequency is sensitive to both V_F and t_d, so the simultaneous (weighted) evaluation of both causes some spread in the extracted V_F value; the cost function is very shallow along this axis (i.e. for different relative weights of frequency and duty cycle error), leading to slow convergence when changing the weights, and modest variation in parameter values but insignificant change in total error.

t_d = 3.57μs and V_F = 1.162V were found, with an error of 1.178kHz RMS and 2.868kHz peak for frequency, and 1.877% RMS and 6.42% peak for duty cycle. The time delay comports well with expectations; the rectifier voltage seems suspiciously high for an MBR160, though.

Discussion

Given the small number of data points relative to the number of parameters, the quadratic case is likely quite sensitive to noise in the measurements; the exact values of parameters probably shouldn't be taken very seriously. The linear case should be well supported, but may be limited by measurement error (especially outliers), or there may be important terms missing from the analysis that could better explain the discrepancy with the derived formula. Several points are distinct outliers, across multiple analyses; I was not able to find any reliable correlations to explain them. This includes repeating measurements on (or very near) several points.

Some measurement errors can be identified: oscilloscope measurements are limited by (circuit, ambient and acquisition) noise, bandwidth, and exact wave shape. Frequency of the circuit itself is a bit unstable, with a natural variance in the 0.1kHz range (two decimal points were written down where possible, crudely estimating the mean value by eye). Peak readings are susceptible to wire and probe placement near L1's stray fields (a shielded type might've been more wisely chosen), its square-wave voltage and edge ringing having a noticeable impact on VR1 peak voltage. DMM measurements are a bit inconsistent as they sometimes seem to read correctly right away, and other times take several seconds to settle (but never more than 1% or so off on the initial reading). The circuit itself is susceptible to thermal drift, particularly V_F (the loose diode heating up significantly at high I_o and low V_o), and V_o (a crude shunt regulator was used as the load, a "rubber diode" using an IRLI3615 with D-G-S potentiometer). Finally, the breadboard itself, through loose arching wires, dubious contacts, dirty/oxidized wires, etc., seems to produce many inconsistencies; occasionally I see frequency jump by a couple kHz, sometimes in relation to wire position (in particular, VR2), but other times unrepeatable, presumably due to loose contacts. Some of these errors will be persistent, systematic; others inconsistent, with variances large (breadboard contacts?) to small (instrument error). A PCB would be needed to address many of these errors, and an automatic DAQ system would greatly enhance gathering of data.

A few additional points were taken with better-performing components: C9 = 220pF and Q5 = IRFZ34N. Efficiency seems improved, including a somewhat lower V_F = 0.956V, and a reasonable t_d = 2.56μs. Frequency and duty cycle fitness are better; I_o fitness is slightly better (error 0.0177A RMS), though hardly unexpected from the small number of points.

Also, some comments about phase, that don't really fit anywhere else: the small-signal response from V_ref to I_o was investigated some. As expected, injection locking occurs for large amplitudes, and for test frequencies close to F_SW. For small amplitudes, and away from F_SW (and harmonics, and subharmonics thereof), the small-signal response can still be measured. Method: C4's "low" end was lifted from GND, instead connected to a 50Ω signal generator, driving a sine wave of variable frequency (say 1-50kHz) and low amplitude (10s mV). With oscilloscope trigger on the generator's sync output, 128× averaging was used to reduce switching ripple at RS1 and reveal the perturbation. It was found that gain is fairly constant up to F_SW, dropping by perhaps 10-20% before lock-in occurs. Phase is remarkably flat; evidently, the hysteretic controller has essentially ideal response time. Which, more or less makes sense, I mean it kind of can't be any faster and still be a switching amplifier. Above F_SW, phase inverts (going to near 180°), and amplitude drops off quickly. I didn't see it worthwhile/necessary to draw a Bode plot here, and I'm not really sure how best to express the lock-in phenomenon in that format (hey, it's a linear plot of a nonlinear system, how much sense is it supposed to make?). Anyway, I wanted to fit in this observation somewhere, and plain text will do.

In all, it seems the equations are adequate for back-of-the-envelope level figures: there's certainly ballpark agreement between predicted and measured parameters. It's not obvious how sensitive these results are to particular component values, or other system properties (like rise/fall time), and if they vary proportionally as the equations suggest. It would be good to evaluate changes in these variables—but this will take dozens more data points to explore, and I don't particularly need to go that in-depth with this circuit, so I will leave it here. As a design process, assuming the equations as correct is as good as anything else, but precise results will need to be measured in a real circuit.

The data are compiled into a spreadsheet, along with various calculations: Hysteretic_Control_Data.xlsx The SOLVER extension is required to evaluate the regression parameters. No particular effort was put into commentating blocks, or formulas; this is just a very basic spreadsheet, and the formulas are presented as-is or "self-documenting". Nor have I made any effort to format the data inline here (the above tables are mess enough as it is :) ).

Combined Feedback

The current output is great for certain loads already, LEDs for example, but what if we want regulated voltage, or something inbetween, a more resistive / Thévenin source perhaps?

Now that we have a three-port average-mode model (with essentially flat gain up to F_SW), we can play with it: embed it in other circuits as a building block, see what happens.

Voltage Follower Equivalent Circuit

First, we modify the earlier circuit slightly, by taking in a difference voltage: V_ref → V_ref − V_f. Connecting V_f to a voltage divider, we obtain three equations: the input difference, the sum of currents on node VO, and the resistor divider. We can also assume some load resistance R_L on the output. In the Laplace domain, this gives,

$G_{ref} \left( V_{ref} - V_o \frac{R_{f2}}{R_{f1} + R_{f2}} \right) + G_{in} V_{in} + I_{offs} = V_o \left( \frac{1}{R_o} + \frac{1}{R_L} + sC \right)$

(Assuming R_fs are large enough to ignore.) Note that R_o = 1/G_o is simply in parallel with R_L, so we can use the total Thévenin equivalent resistance on this node, R_th. Removing the independent terms (V_in, I_offs, and any independent load current), and rearranging to the transfer function, we get:

$H(s) = \frac{V_o(s)}{V_{ref}(s)} = \frac{G_{ref} R_{eq}}{1 + s R_{eq} C} \, , \ \, R_{eq} = \frac{ R_{th} }{ 1 + G_{ref} R_{th} \frac{R_{f2}}{R_{f1} + R_{f2}} }$

This gives us an expected DC gain (s → 0) of G_ref R_eq, which in turn, if G_ref → ∞, reduces to (R_f1 + R_f2) / R_f2, the ideal voltage gain for a noninverting op-amp circuit. Note that, in the same (G_ref) condition, bandwidth goes to infinity—this cannot actually happen in practice of course, response is limited by the LC output filter; the above assumes an ideal converter for all frequencies (whereas small-signal or real practical bandwidth ends somewhat less than F_SW), so we shall take this to mean, as soon as the input changes, the output latches on solidly until the commanded level has been reached; in other words, we've removed the current-mode aspect and made a pure voltage-mode hysteretic converter (and so, we should put the inductor back into the model, and start the whole operational analysis from the top, as both L and C elements are in the oscillation loop and affect operating frequency and stability). At the other extreme, if we take R_f2 → 0, H(s) is proportional to R_th, i.e. we have a constant-current source. We thus have a continuum between two extremes, and can vary the output resistance from nearly-pure current, to nearly pure voltage, by suitable design choices.

About V_in Current

I would be remiss to completely ignore this parameter. I didn't set up to measure current in the experimental section, nor have I made any expression for it yet. I tested with a fixed supply, and the voltage coefficient is small anyway, so it's a low priority. Still, it is a control input, and as it draws substantial (and dependent) current, a nonzero source impedance to this port is another mechanism for feedback to occur.

Clearly, given it's a buck converter, VIN must draw at least the output power, and we could simply take that, plus some efficiency cost (switching and conduction losses, say), and draw the corresponding current. Hand-wavey, but likely to be close enough. This gives us a current proportional to output, but inversely proportional to voltage. Which, surprisingly, is our first (external, averaged) nonlinearity, despite the manifest nonlinearity internal to the hysteretic controller itself!

Taking that hand-wave approximation, we have I_in = V_oI_o / V_in, which must be linearized around the operating point. We take the partial derivative with respect to each variable:

$\frac{\partial I_{in}}{\partial I_o} = \frac{V_o}{V_{in}} \quad \ \frac{\partial I_{in}}{\partial V_o} = \frac{I_o}{V_{in}} \quad \ \frac{\partial I_{in}}{\partial V_{in}} = -\frac{I_o V_o}{{V_{in}}^2}$

The linearized (small-signal) current is then the sum of all partials times the respective (AC) signals. Note that the self-impedance ∂V_in/∂I_in is negative, and this is not a mistake of current convention: the input resistance is negative because the converter has a constant-power characteristic.

We now have a proper port as such: a partition through a circuit, at a single node (with respect to common), where the voltage on and current through that node is defined, and to which a connection can be made. If we connect a one-port such as a resistor or capacitor, we can substitute that V/I function through the port, and reduce the system from a three-port down to two: just V_ref and V_o (and their currents; note that I_ref remains trivial i.e. zero in this model so far). Or, if we aren't interested in transfer characteristics, but the input or output dynamics, we can set ∂V_ref = 0 and reduce it further to a one-port.

Vin-Vo Two-Port Circuit

Drawing out the two-port (V_ref omitted), we find the following equations:

$i_{in} = v_o \frac{I_o}{V_{in}} + i_o \frac{V_o}{V_{in}} - v_{in} \frac{V_o I_o}{{V_{in}}^2} \ , \quad v_{in} = i_{in} \left( R_r + \frac{1}{sC_r} \right) \ , \quad i_o = -v_o \frac{t_d}{L} + v_{in} \frac{t_d}{2L}$

Or whatever combinations of input and output network one sees fit. Note the convention of using lower-case symbols to refer to small-signal quantities, and capitals for their steady-state (DC) values. Substituting to eliminate the V_in port, we can obtain an expression for, for example, the output impedance $Z_o = \frac{\partial v_o}{-\partial i_o}$ (note negation due to sign convention at the output), and observe the effect of the input/supply network, and other parameters.

Solving for these equations is left as an exercise for the reader; mainly because ~~I probably made an algebra mistake somewhere~~ as established earlier, these symbolic models aren't a great fit to the real thing—in the ballpark, but far from exact—so the validity or veracity of these relations leaves something to be desired.

Closing Remarks

A simple yet effective controller has been demonstrated; exploring the operating equations, we have found a simple system both in theory and in practice, easy to solve and to design. A scale model was designed, built and tested, and found to roughly obey the control law established in theory. Experimental shortcomings likely limited the fitness of the measurements, but theoretical oversights may still play a role. Finally, a multi-port linearized model was envisaged; stopping short of a fully fleshed-out model, the method is at least touched upon, and with some effort, a complete model can be built given the background here. Finally, in the overarching context of the load dump generator, the simple control laws seem encouraging, and straightforward design and testing is expected.

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